{"id":15840,"date":"2022-02-25T14:21:56","date_gmt":"2022-02-25T14:21:56","guid":{"rendered":"https:\/\/cit.upc.edu\/?post_type=portfolio&p=15840"},"modified":"2023-07-11T11:29:27","modified_gmt":"2023-07-11T11:29:27","slug":"cocounit-els-processadors-del-futur-per-a-la-computacio-cognitiva","status":"publish","type":"portfolio","link":"https:\/\/cit.upc.edu\/ca\/portfolio-item\/cocounit-els-processadors-del-futur-per-a-la-computacio-cognitiva\/","title":{"rendered":"CoCoUnit: Els processadors del futur per a la computaci\u00f3 cognitiva"},"content":{"rendered":"\n

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El grup de recerca Architectures and Compilers (ARCO) treballa en el projecte CoCoUnit, per dissenyar noves arquitectures de sistemes de computaci\u00f3 que siguin energ\u00e8ticament eficients especialment per a aplicacions que facin \u00fas intens de funcionalitats cognitives, com ara el reconeixement de la veu, la traducci\u00f3 autom\u00e0tica , la s\u00edntesi de veu, la classificaci\u00f3 d\\’imatges o el reconeixement d\\’objectes.<\/h4>
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Se segueix un enfocament disruptiu mitjan\u00e7ant la recerca en arquitectures no convencionals que milloren dr\u00e0sticament l\\’efici\u00e8ncia energ\u00e8tica i alhora aporten millores substancials en el rendiment. Aquestes plataformes utilitzen diversos tipus d\\’unitats especialitzades per a diversos camps, i es fa un \u00e8mfasi especial en processadors gr\u00e0fics i arquitectures inspirades en el cervell (per exemple, xarxes neuronals) a causa del seu potencial per explotar paral\u00b7lelisme massiu i la seva elevada efici\u00e8ncia energ\u00e8tica. Es proposen extensions a les arquitectures existents combinades amb nous acceleradors i unitats funcionals. El resultat final d\\’aquest projecte \u00e9s idear plataformes que proporcionin noves experi\u00e8ncies als usuaris en les \u00e0rees de computaci\u00f3 cognitiva i intel\u00b7lig\u00e8ncia computacional tant en dispositius m\u00f2bils com en servidors i centres de dades.\r
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El projecte est\u00e0 aproximadament al seu equador. Entre els resultats m\u00e9s rellevants fins ara cal destacar:\r
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\tEl disseny d\\’un \u201cSystem-on-Chip\u201d que inclou diversos acceleradors per al reconeixement autom\u00e0tic de la parla en temps real i baix consum energ\u00e8tic.\r
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\tEl disseny d\\’un accelerador per a xarxes neuronals que inclou t\u00e8cniques noves per reduir el consum d\\’energia, com s\u00f3n el re\u00fas de c\u00f2mputs, la poda de neurones i connexions, la selecci\u00f3 din\u00e0mica de la precisi\u00f3 utilitzada en els c\u00e0lculs, l\\’augment de la localitat als accessos a mem\u00f2ria, i un nou mecanisme per planificar l\\’execuci\u00f3 concurrent de m\u00faltiples inst\u00e0ncies de xarxes neuronals recurrents.\r
\tUna caracteritzaci\u00f3 detallada del rendiment i consum energ\u00e8tic dels sistemes de computaci\u00f3 per a vehicles aut\u00f2noms i la proposta d\\’un accelerador per optimitzar un dels seus colls d\\’ampolla principals, la localitzaci\u00f3 i el mapeig simultani (SLAM).\r
\tEl disseny d\\’una nova unitat per millorar el rendiment de les GPU per a algoritmes de grafs mitjan\u00e7ant la fusi\u00f3 i filtratge dels accessos a mem\u00f2ria.\r
\tNoves microarquitectures per a processadors gr\u00e0fics de baix consum basades a explotar la coher\u00e8ncia entre frames successius per evitar c\u00f2mputs i millorar-ne l\\’efici\u00e8ncia energ\u00e8tica d\\’una forma substancial, aix\u00ed com noves organitzacions de la seva jerarquia de mem\u00f2ria per explotar millor la localitat als accessos.\r
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